Static random access memories (SRAMs) are important components in microprocessor chips and applications, and the portion of SRAM arrays in the total chip area has continued to increase. As devices are scaled down, process variations, including device random fluctuations, are key factors in SRAM design. Furthermore, devices in SRAM cells are being aggressively scaled in terms of device width (or other characteristic dimension) to reduce the area. The smaller cell area aggravates random statistical fluctuations, and hence stable SRAM design is more challenging and complex as silicon technology is advanced.
SRAM cells can be quite unstable in READ operations, since the data in the storage node is disturbed by the READ current, which can flip the logic values in the storage nodes VL, VR, FIG. 1 shows a READ operation in a prior-art SRAM cell 100. The voltage on node VR rises above zero to a voltage determined by the resistive voltage divider for the access devices 102, 104 (AL and AR) and pull-down devices 106, 108 (NL and NR). Hence, wider pull-down devices 106, 108 (NL and NR) relative to access devices 102, 104 (AL and AR) must be used to improve the READ mar gin (or to achieve a successful and reliable READ operation). The construction and operation of conventional cell 100, including true and complementary bit lines 110, 112; word line 114, and transistors 116, 118 (PL and PR) is well-known to the skilled artisan.
The WRITE operation is also very unstable in prior-art cells due to increased process variations. FIG. 2 shows a WRITE operation in the prior-art SRAM cell 100 (elements in FIG. 2 similar to those in FIG. 1 are designated by the same reference characters) In the WRITE operation, devices 102, 116 (AL and PL) (or devices 104, 118 (AR and PR)) form a resistive voltage divider fox the lower-voltage bit line 110 (BL) and the node (VL) having a logical “one” stored therein. In this case, device 102 (AL) (or device 104 (AR)) must be stronger than device 116 (PL) (or device 118 (PR)) to improve the WRITE margin (that is, to enable a quick exchange of the state of the stored data between the two cell nodes, VL and VR).
Double-gate (DG) complementary metal oxide semiconductor (CMOS) devices offer distinct advantages for scaling, due to much reduced short-channel effects, and DG CMOS also offers the opportunity to proceed beyond the performance of single-gate (SG) devices such as bulk silicon or silicon-on-insulator (SOI) A variety of DG device structures including FinFEI, TriGate, and gate-all-around field effect transistors (FETs) are proposed. Among these, the FinFET is quite promising due to its easy fabrication and process flow, and its superior performance. FIG. 3 shows a FinFET device structure and FIG. 4 shows a cross-sectional view, as known from E. J. Nowak, et al, “A Functional FinFET-DGCMOS SRAM Cell,” IEDM. Tech Dig., pp. 411-414, December 2002. A FinFET device 300 can include multiple fins forming sources 302 and drains 304 with a central gate structure 306; as best seen in the insets in FIG. 3, first and second (or front and back) gates 307, 308 are formed for each fin. As best seen in FIG. 4, device parameters include the oxide thickness for the front and back gates, toxf and toxb, and the dimension between the gates tSi. Each gate controls a separate channel.
Interestingly, DG FinFET devices can be employed either with two gates tied, as shown in FIG. 5, or independently-biased, as shown in FIG. 6, and as known from Y. Liu, et al., “A High Threshold Voltage-Controllable 4I FinFET with an 8.5-nm-Thick Si-Fin Channel, IEEE Elec. Dev. Lett., Vol. 25, No. 7, pp. 510-512, July 2004, and Chiang, et al., “Novel High-Density Low-Power High-Performance Double-Gate Logic Techniques,” Proc IEEE Internat SOI Conf, Charleston, S.C., October 2004. Similar elements in FIGS. 3 through 6 have received the same reference characters.
One way to improve SRAM READ/WRITE margins is to use the just-mentioned independently-controlled gates. Reference should now be had to ICGS 7 and 8, wherein elements similar to FIGS. 1 and 2 have received the same reference character incremented by six hundred (FIG. 7) and seven hundred (FIG. 8); note that double-gate FETs are depicted in FIGS. 7 and 8. Yamaoka developed a “Yin-Yang” feedback technique for SRAM cells to improve the READ stability, as shown in FIG. 7 and as known from M. Yamaoka, et al., “Low-Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell,” Symp VLSI Circuits Dig., pp. 288-291, June 2004 The main drawback of the device of FIG. 7 is that the WRITE margin cannot be improved due to the reduction of the strength for the access devices 702, 704, because the access devices are in a single-gate (SC) mode of operation (back gates grounded) for the “Ying-Yang” scheme. Guo developed a scheme to connect the back gate of the access device and the corresponding storage node, as shown in FIG. 8 and as known from Z. Guo, “FinFET-Based SRAM Design,” Proc. Internat Symp Lower Power Elec. Des., pp. 2-7, August 2005. The back gate of device 802 is connected to left-hand node 890 and that of device 804 is connected to light-hand node 892. However, the scheme of FIG. 8 exhibits several drawbacks. First, the WRITE margin is not improved because both access devices 802, 804 and pull-up devices 816, 818 are in DG device mode during the WRITE operation, where the strength of the access device relative to the pull-up device is not improved, just as in the scheme of FIG. 7. Second, in a half selected WRITE mode, the scheme of FIG. 8 has a serious problem due to the unwanted large leakage current flow from the storage node (storing a logical “one”) to the bit line (at ground voltage) because the back gates are biased to VDD. Under conditions of increased threshold voltage (Vt) variation, WRITE operations will be unstable for this scheme.
In summary, for prior art cells, the conventional scaled 6T cell of FIGS. 1 and 2 is not stable; in the schemes of FIGS. 7 and 8, the WRITE margin is not improved; and writing is unstable in the half-selected case for the scheme of FIG. 8. It would be desirable to overcome one or more of the limitations in previous approaches.